1. Field
Embodiments of the present invention relate to a semiconductor apparatus, and more particularly, to a memory apparatus including multi-level memory cells.
2. Description of the Related Art
A conventional DRAM includes a memory cell implemented with a capacitor, and stores data by charging or discharging electric charges into or from the capacitor of the memory cell. However, data stored in a DRAM is volatile because a leakage current exists due to the characteristic of the capacitor. In order to avoid disadvantages resulting from the volatile characteristic of the DRAM, nonvolatile memories, which do not require data retention, have been developed. In particular, attempts to implement nonvolatility by changing a memory cell structure have been made. A representative example of the nonvolatile memories is a resistive memory apparatus, which includes resistive memory cells.
FIG. 1 schematically illustrates a conventional resistive memory apparatus. The conventional resistive memory apparatus includes a memory cell 10 and a transistor N1. The memory cell 10 is formed of a resistive material. A resistance value of the resistive material changes according to a temperature of the memory cell 10 or a current flowing through the memory cell 10. The memory cell 10 has a different resistance value depending on data stored therein.
The transistor N1 is coupled to the memory cell 10, and provides a sensing current to the memory cell 10 so as to sense the data stored in the memory cell 10. The transistor N1 applies a power supply voltage VPPSA to a sensing node SAI in response to a bias voltage VB.
The conventional resistive memory apparatus changes a voltage level of the sensing node SAI to sense the data stored in the memory cell 10. When the bias voltage VB is applied, the transistor N1 is turned on to provide a predetermined current to the sensing node SAI. The predetermined current provided to the sensing node SAI flows through the memory cell 10. Thus, the voltage level of the sensing node SAI changes depending on the resistance value of the memory cell 10. When the memory cell 10 has a large resistance value, the sensing node SAI has a high voltage level, and when the memory cell 10 has a small resistance value, the sensing node SAI has a low voltage level. As such, the conventional resistive memory apparatus provides the predetermined current to the sensing node SAI, and senses the data stored in the memory cell 10 based on the change in the voltage level of the sensing node SAI depending on the resistance value of the memory cell 10.
In order to reliably sense the change in the voltage level of the sensing node SAI depending on the resistance value of the memory cell 10, a boosting voltage VPPSA is used as the power supply voltage. A boosting voltage VPPSA having a higher level than an external voltage may be generated through a pumping circuit or the like.